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Digital Design and Verification Engineer (m/w/d)

In our dynamic and rapid growing group with headquarters in Eindhoven (NL) and locations in Reutlingen (D), Stutensee (D), Pisa (I) and Shanghai (CHN), ca. 110 employees work hard to support our customers in Automotive and High-Tech Industry.

In our team in Stutensee, we look forward to your support as

Digital Design and Verification Engineer (m/w/d)


Key tasks / Key responsibilities

  • Module level digital design and implementation on RTL level (System Verilog) regarding power optimized synthesis, assertion-based verification, design for test of proprietary CPUs, serial interfaces, state machines and sequencer for signal generation & measurement
  • Create test benches on module and system level for functional as well as metric driven verification and enable constrained random regression tests
  • Synthesize designs optimized for power (clock gating), test (scan path insertion) and reliability (fault-tolerance and fault-recovery), insert clock trees, verify the netlist for logic equivalence (LEC), static timing (STA) and cross domain clocking (CDC)
  • Verify final netlist according acceptance criteriums including back annotated regression tests and release netlist together with technical lead to fab and mask production
  • Maintain, enhance and optimize synthesis and verification scripts
  • Generate automatically test pattern and optimize wafer sort and final test together with test development engineer and technical lead
  • Documentation and support over complete IP development cycle
  • Support lab validation engineers and analyze validation results


Qualifications / Skills

  • Successfully completed studies in the field of electrical engineering, microelectronics or a comparable qualification
  • Experience in digital integrated circuit design and/or verification
  • Expertise in RTL coding
  • Hands on experience in
    o Functional and assertion-based verification
    o Design for (DFT), test scan insertion and ATPG
    o Timing analysis, CDC and LEC
  • Experience on technology background and backend gate level implementation is beneficial
  • Experience in Digital Layout and Digital on Top methods is beneficial
  • Hands on experience with CPU structures and non-volatile memories is beneficial
  • Good communication skills in English and German

Would you like to join our team?

Please send your CV with motivation letter including earliest starting date and salary expectations to careers@sciosense.com. For further information please contact our HR Manager Remco Spooren – Tel. +31 6 89 93 52 66.

Apply now